The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
An integrated circuit is fabricated by performing multiple formation and removal processes based on a set of masks. The set of masks are prepared based on a layout design of the integrated circuit, which includes layers of layout patterns illustrating the sizes and shapes of various features of the integrated circuit. The layout design can include a plurality of layout layers for forming electrical components and a plurality of layout layers for forming an interconnection structure electrically connecting the electrical components. In some applications, the layout design is generated by executing a placement-and-routing program based on a circuit schematic of the integrated circuit. In addition to the layout patterns for forming the circuit components as indicated in the circuit schematic, in some applications, layout for forming spare circuit cells are also added to the layout design of the integrated circuit. A spare circuit cell (or also simplified as a “spare cell” in this disclosure) is a circuit cell that does not correspond to any portion of an initial circuit schematic. However, one or more spare cells can be modified or electrically connected with other electrically components when the circuit schematic is modified in order to fix a design flaw or to add or to improve a function of the integrated circuit based on an engineering change order. Although the circuit schematic can be changed to activate spare cells in a modified design, conventionally such modification necessitates the redesign of one or more relatively expensive masks.